`timescale 1ns / 1ps
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// Company: 
// Engineer: 
// 
// Create Date:    11:07:11 11/19/2020 
// Design Name: 
// Module Name:    alu 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
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module alu(
    input [31:0] a1,
    input [31:0] a2,
    input [1:0] aluOp,
    output reg [31:0] aluResult,
    output zero
    );
	
	always @*
	begin
		case (aluOp)
			2'b00:
				aluResult <= $signed(a1) + $signed(a2);
			2'b01:
				aluResult <= $signed(a1) - $signed(a2);
			2'b10:
				aluResult <= a1 | a2;
			2'b11:
				aluResult <= a1 | a2;
			default:
				aluResult <= 0;
		endcase
	end

	assign zero = (a1==a2);
	
endmodule
